1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to formation of a low resistivity gate conductor in a semiconductor gate stack.
2. Related Art
Increased performance of circuit devices on a substrate (e.g., integrated circuit (IC) transistors, resistors, capacitors, etc. on a semiconductor (e.g., silicon) substrate) is typically a major factor considered during design, manufacture, and operation of those devices. For example, during design and manufacture of metal oxide semiconductor (MOS) transistor semiconductor devices, such as those used in a complementary metal oxide semiconductor (CMOS), it is often desired to increase movement of electrons in N-type MOS device (NMOS) channels and to increase movement of positive charged holes in P-type MOS device (PMOS) channels. In addition, during such design, it is often also desired to reduce the depletion of carriers in an area of the NMOS and PMOS device gate electrodes near the dielectric materials during inversion, while minimizing parasitic resistance, and providing an appropriately large threshold or voltage.
Furthermore, it is desirous to manufacture smaller transistors to increase the component density on an integrated circuit. It is also desirous to reduce the size of integrated circuit structures, such as vias, conductive lines, capacitors, resistors, isolation structures, contacts, interconnects, etc. For example, manufacturing a transistor having a reduced gate length (a reduced width of the gate conductor) can have significant benefits. Gate conductors with reduced widths can be formed more closely together, thereby increasing the transistor density on the IC. Further, gate conductors with reduced widths allow smaller transistors to be designed, thereby increasing speed and reducing power requirements for the transistors.
One device structure which has been found to provide good device characteristics such as breakdown voltage, output currents, and pinch-off voltage is a double recessed transistor, an example of which is shown by FIGS. 1-3. As shown first in FIG. 1, a prior art device 10 includes a plurality of trenches 12 and 14 formed in a dielectric material 16, for example, via a replacement metal gate (RMG) process. Dielectric material 16 is removed, and metal layers 18 and 20 are formed within trenches 12 and 14, respectively. In one example, metal layer 18 is a p-metal, which may include tungsten (W) surrounded by titanium nitride (TiN). Metal layer 20 is an n-metal, which may include W surrounded by TiN and titanium carbide (TiC).
Next, as shown in FIG. 2, a barrier layer (e.g., TiN) 24 is formed over metal layers 18 and 20, a pair of spacers 19, and over dielectric material 16 (e.g., by introducing a combination of WF6, a nitrogen-containing gas, H2, and a plasma). Barrier layer 24 is conventionally a layer of metallic material (e.g., TiN, due to its high selectivity to the IDL etch process), or a dielectric material that is employed as a masking layer. Barrier layer 24 may also be a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, or a combination thereof.
A high resistance nucleation layer 26 is then formed over barrier layer 24 (e.g., by introducing a combination of WF6, H2 and a plasma), and a W fill 28 is deposited over nucleation layer 26 within trenches 12 and 14 to form gate conductors. Conventionally, a SiH4+WF6, or B2H6+WF6 step is used for depositing nucleation layer 26 for subsequent thermal CVD-W formation. However, for thin W layers, e.g., less than 100 nanometers thick, such as in W gate stacks, the incorporation of nucleation layer 26 causes higher sheet resistance. This becomes particularly undesirable because the trend for future devices is to have gates with smaller gate lengths and lower resistivity. Furthermore, because the nucleation layer SiH4+WF6, or B2H6+WF6 step is thermally driven, the nucleation property is substrate dependent. This results in rough surface morphology on certain substrates, such as TiN. Rough surface morphology is not desirable because it will affect the subsequent patterning steps required for fabricating gate structures.
Next, W fill 28 is etched, forming the structure shown in FIG. 3. As a result of this process, only a small portion of conductive W fill 28 remains in trenches 12 and 14 following the etch process, which contributes to poor conductance of signal lines and results in signal delay and poor sensing in static random access memory (SRAM). Thus, good conduction of gate lines is very important in future fine feature devices.
As such, current art approaches are inadequate for at least the reasons described above.